M6 chip analysis reveals 2nm process, three-tier CPU cores, doubled Neural Engine

Key points

Apple's M6 chip is its first to use TSMC's 2nm manufacturing process with GAAFET transistors.

The M6 CPU features two Super cores, four Performance cores, and six Efficiency cores, with a shared 20 MB L2 cache.

The M6 GPU has 12 cores, a 20 per cent peak performance increase over the M5, but memory bandwidth tops out at 170 GB/s.

A die-shot analysis of Apple’s M6 chip has laid bare its architectural design, revealing a 2nm manufacturing process, a three-tier CPU core layout and a doubled Neural Engine. The die shots come from High Yield and SemiAnalysis, and the findings were summarised by Macworld. As Apple announced on 25 August, the M6 is its first 2nm chip, built on TSMC’s new node with gate-all-around field-effect transistor (GAAFET) technology. The die measures approximately 142 mm², down from 157 mm² for the M5.

The CPU comprises two Super cores, four Performance cores and six Efficiency cores. The Performance cores are roughly half the size of the Super cores. Each Super core has its own 1.5 MB L2 cache, while a shared 20 MB L2 cache serves the rest — up from 16 MB on the M5. The system-level cache remains at 16 MB. The Efficiency cores are identical to those in the A20 Pro and have their own separate L2 cache and AMX unit.

The GPU has 12 cores, up from 10 in the M5, delivering a 20 per cent increase in peak compute performance. However, memory bandwidth is limited: Apple quotes up to 170 GB/s, available on 24 GB and 32 GB configurations using LPDDR5x at 10,667 MT/s, while the 16 GB model manages 153 GB/s (9,600 MT/s) — the same as the M5. The Neural Engine is doubled, with two separate 16-core units each possessing its own cache.

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